A solid state drive (SSD) is designed to provide reliable and high performance storage of user data across a flash-based memory system containing a host interface controller (such as a Serial Advanced Technology Attachment (SATA)) interface) and a number of memory multi-chip packages (MCPs), where each MCP contains a stack of NAND flash dies and, optionally, a flash memory controller. The Open NAND Flash Interface (ONFI) protocol provides support for parallel access to multiple NAND dies (or “logical units” (LUNs)) on a single “target” or NAND multi-chip stack on a single shared ONFI channel. In a typical SATA-based SSD application, a central host controller accesses multiple attached devices (targets/NAND device clusters) on each ONFI channel, and across several ONFI channels. (A typical host controller would include a SATA interface and four, eight, or more flash interface channels. These channels may utilize a standard flash interface protocol, such as ONFI.) Each ONFI target typically controls 2, 4, or 8 NAND dies.
Multiple flash technology types (one-, two-, and three-bits per cell, for example) and mixed-technology flash devices (devices with binary regions in an otherwise multi-level cell device) are available; however, some industry standard protocols, such as ONFI, only support commands for a single memory type, as they assume that all the memory devices in an MCP are homogeneous. For example, ONFI interfaces assume that all of the memory devices in the multi-chip package are X1 (one bit per cell), X2 (two bits per cell), or X3 (three bits per cell). However, in some applications, it may be desired to have mixed technology devices (i.e., memory devices of different types) and/or mixed technology targets (i.e., a memory device with different memory types in different address ranges).